Feb 6 2025
SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable source of truth, SystemRDL provides a basis on which you can build other assets, such as SystemVerilog designs, test suites, software (drivers), and documentation. Read more
Jan 22 2025
The Texas Instruments MSP430 is a family of MCUs with its own custom ISA that enables ultra-low-power use cases. With a long history of supporting a breadth of products, including devices deployed in space, the most popular applications include performing highly reliable analog measurement functions, building automation and battery-management solutions as well as highly reliable IoT installations, and at Antmicro, we work with the MCU when developing power-constrained devices for our customers. Read more
Dec 31 2024
Renode is typically used to test and debug complex hardware-software systems, where having a tight interactive debugging feedback loop and a visual overview of the state of the system and registers are key. Renode’s superpower is making embedded systems more like working with regular software by representing your entire system within a single deterministic simulation environment that can be more easily integrated with typical continuous integration based workflows. Read more
Oct 16 2024
Testing in simulation is a great way to enable parallel development of software and hardware and ensure quality standards starting early into your project. Renode, Antmicro’s open source simulation framework provides a deterministic development environment with a constantly expanding portfolio of integrations for designing advanced test suites, co-simulation capabilities, as well as simulation models for hundreds of HW blocks, SoCs and boards. Read more
Oct 1 2024
Although cache modeling is usually not part of ISS level simulation, there are cases where it’s crucial to understand memory access patterns e.g., when building a new chip and deciding on cache size and layout, or working on low-level, time-critical firmware that requires precise cache management. Since Antmicro’s open source Renode simulation framework is often used for architectural exploration thanks to its broad ISA support, and already includes advanced execution tracing options, we’ve expanded its capabilities with trace-based cache usage evaluation. By utilizing Renode’s execution tracing data, it is possible to gain detailed insights into cache behavior, such as cache hits, misses, and the overall hit ratio, which in turn enables precise analysis of how different cache configurations impact system performance, as well as identification of bottlenecks and opportunities for optimization. Read more