Real time applications such as space or automotive where instant autonomous decision making is crucial require configurable standardized interrupt controllers. There are many well-known examples such as the Global Interrupt Controller (GIC) for Cortex-A, Nested Vectored Interrupt Controller (NVIC) for Cortex-M, Platform Level Interrupt Controller (PLIC) or Core Local Interruptor (CLINT) for RISC‑V, etc., and some vendors introduce their own custom interrupt controllers working on top of the standard ones.

To enable more advanced use cases, on top of PLIC and CLINT that have been available so far, the new Core-Local Interrupt Controller (CLIC) fast interrupts standard has been developed for the RISC‑V ISA. Given Antmicro’s broad work with RISC‑V and comprehensive support for the standard in our open source Renode simulation framework, adding a CLIC model to our tool was just a matter of time.

The new CLIC specification provides for a range of features that are helpful for low-latency interrupt handling, such as configurable interrupt priority, preemption and selective hardware vectoring. RISC‑V platforms can use both the legacy CLINT and the new CLIC interrupt controllers, and Renode allows the possibility of dynamically switching between these modes.

In this article, we will describe the new features that CLIC offers and the inner workings of the new CLIC model in Renode simulation. By making a CLIC model available before the formal ratification in the RISC‑V specification, Renode offers a way for semiconductor companies and hyperscalers to get a head start in the development race to incorporate RISC‑V in products leveraging fast interrupts.

Simulating CLIC-enabled RISC‑V devices in Renode

The CLIC specification in RISC‑V is designed to provide for low-latency and pre-emptive interrupts for RISC‑V systems and is aimed to be a flexible alternative to existing interrupt controllers while keeping hardware implementations relatively simple. CLIC itself allows software to control interrupt mode, trigger type and priority while also providing a CLIC mode vectoring behavior for each individual interrupt. In addition, CLIC provides support for decreasing the number of accesses in an interrupt handler through independently configurable hardware vectoring for each interrupt.

Renode now ships with a configurable CLIC model that can be trivially added to the virtual representation of your in-development SoC and parametrized as needed. For example, to set up a basic RISC‑V CPU in Renode with CLIC support, you only need to define it in a .repl (REnode PLatform) file, e.g.:

cpu: CPU.RiscV32 @ sysbus
    [...]
    privilegedArchitecture: PrivilegedArchitecture.PrivUnratified

clic: IRQControllers.CoreLocalInterruptController @ {
        sysbus <0x04000000, +0x10000>;
        cpu <0x1000, +0x4A1>
    }
    cpu: cpu
    machineLevelBits: 8 
    supervisorLevelBits: 8
    modeBits: 0

The parameters in the .repl file can be freely adjusted, which provides flexibility for users to experiment with different configurations and inform their hardware development process. For example, the specification for the CLIC declares a parameter defining the split between interrupt level and priority in the interrupt attribute register, easily configurable on both the machine and supervisor level.

Other parameters are also modifiable in the .repl file according to need, such as adding more cores or changing the modeBits parameter, responsible for setting how many bits are used to configure the interrupt mode. modeBits corresponds to cliccfg.nmbits in the CLIC specification and encodes how many bits are used to represent mode when configuring an interrupt. This setting can vary between 0 (all interrupts are in Machine mode), 1 (interrupts can switch between Machine/Supervisor) and 2 (interrupts can switch between Machine, Supervisor and User modes).

Testing the CLIC implementation in Renode

The correctness of the CLIC implementation in Renode was tested using external software samples which are proposed to be included in the official RISC‑V Architecture Test and which are already part of Renode’s own Robot tests. These tests have also been cross-checked with the results from the RISC‑V Sail Model.

To run the complete suite of Robot tests by yourself in Renode (assuming you are in the main Renode directory), use:

renode-test tests/peripherals/CLIC/*.robot

This contains CLIC-related RISC‑V Architecture Tests converted to Robot, as well as several tests that we developed for the purpose of testing the CLIC model.

The early support of CLIC in Renode allows for the development of software that takes advantage of fast interrupts before formal ratification of the specification, while different core and CPU configurations can be rapidly tested in systems including a wide range of peripherals, both those natively supported in Renode or co-simulated using DPI, SystemC and more.

Developing RISC‑V devices for real time applications with Renode

Support for fast RISC‑V interrupts in Renode enables our customers to implement CLIC in parallel to the ratification process, giving them a head start in the development pipeline.

Beyond simulation, Antmicro’s RISC‑V engineering services include customizing and enhancing RISC‑V cores, as well as end-to-end development of RISC‑V-based devices facilitated by our System Designer, a comprehensive framework to help you explore, describe, architect and build products with Antmicro from concept to deployment.

To find out more about how Renode can enable pre-silicon development of your applications, get in touch at contact@antmicro.com.