Mar 18 2024
The "killer feature" of open source is its transformative power in enabling collaborative vertical integration, where instead of building up silos of divergent capabilities, organizations can collaborate freely, combining their strengths and perspectives while remaining in full control of their own fate. Read more
Feb 27 2024
One of the key metrics helping ensure code quality is test coverage, providing objective, automatic ways of making sure that all of the most important branches of the code are verified. Antmicro’s open source Renode simulation framework already offers advanced Python-driven scripting and automation as well as extensive execution tracing features, and the recent addition of code coverage analysis provides developers with even more control and better understanding of their software. Read more
Feb 16 2024
Renode is often used for deterministic and scalable testing of consumer-grade products like in the case of STM32F412 and STM32H743 microcontrollers used in the ChromiumOS’ FPMCU (Fingerprint Firmware) module found in Chromebooks – an effort described in detail in our previous blog note. Read more
Feb 8 2024
While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft can take advantage of a much more advanced and capable data processing infrastructure. The space systems of today are essentially powerful heterogeneous multi-node setups with many layers of redundancy and lots of communication flowing in all directions. The resulting complexity requires rigorous testing in order to predict and prevent possible catastrophic failures - because in space, no one can hear your hardware beep. Read more
Dec 18 2023
Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC‑V ISA being a major focus for both ourselves – as a founding member of RISC‑V International – and our customers, including e.g. Google Research and Microchip. Renode’s support for RISC‑V is also being developed as part of EU-funded research activities such as TRISTAN, to enable easier prototyping and development of new silicon based on open source core and peripheral IP implementations, which we are also heavily involved with. Read more