Oct 1
2024
Although cache modeling is usually not part of ISS level simulation, there are cases where it’s crucial to understand memory access patterns e.g., when building a new chip and deciding on cache size and layout, or working on low-level, time-critical firmware that requires precise cache management. Since Antmicro’s open source Renode simulation framework is often used for architectural exploration thanks to its broad ISA support, and already includes advanced execution tracing options, we’ve expanded its capabilities with trace-based cache usage evaluation. By utilizing Renode’s execution tracing data, it is possible to gain detailed insights into cache behavior, such as cache hits, misses, and the overall hit ratio, which in turn enables precise analysis of how different cache configurations impact system performance, as well as identification of bottlenecks and opportunities for optimization. Read more
Sep 3
2024
Asymmetric multiprocessing (AMP) setups are very common in modern SoCs which mix various types of cores or even architectures to provide sufficient processing power when needed, while keeping the system energy efficient overall. The AMP architecture is especially useful in applications requiring both time-critical and user-facing, high-performance processing, such as automotive. Read more
Aug 29
2024
With very broad support for simulating RISC‑V, Armv8-R and Armv8-A platforms, Renode is addressing the need to target scenarios of increasing complexity, including multi-core, heterogeneous embedded systems or server applications for management, security, Machine Learning acceleration and more. Read more
Jul 9
2024
SystemC is a C++-based system design and verification language and library that allows for modeling of hardware systems, widely used by IP vendors who often provide SystemC-based models for their blocks. Based on community demand, recently we have extended Renode, our open source simulation framework with support for SystemC Transaction Level Modeling (TLM) - a standard SystemC interface designed to drive memory-mapped communication, providing interoperability between various components. By including support for SystemC, we extended the co-simulation integration portfolio of Renode that already includes direct integration with Verilator and a DPI-based interface for multiple simulators. This makes Renode even more accessible for engineering teams interested in pre-silicon development with a mix of custom-made and off-the-shelf blocks. Read more
Jun 24
2024
The openness and customizability of the RISC‑V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger systems, standalone embedded MCUs and even many-core server AI processing solutions. With first-class RISC‑V support and advanced co-simulation capabilities, Renode, Antmicro’s open source simulator, is helping silicon, firmware and software teams be more productive in all of those scenarios. Read more