What's new?

Oct 16 2023

Linux support on 64-bit Cortex-A platforms in Renode for automotive, space and industrial scenarios

Linux support on 64-bit Cortex-A platforms in Renode for automotive, space and industrial scenarios

With the most recent 1.14 release of Renode Antmicro introduced initial support for ARMv8-A, opening the doors to many new use cases. 64-bit Cortex-A cores based on this architecture have been extremely popular in Linux-based devices in areas like embedded and mobile, but are also in widespread use in automotive, space and industrial applications where simulation-based testing is of critical importance. Read more

Oct 5 2023

Fuzzing Zephyr with AFL and Renode

Fuzzing Zephyr with AFL and Renode

Fuzzing is an automated testing technique aimed at detecting problems like crashes or memory leaks in software by feeding it with invalid, often random input. It is especially valuable in safety-critical use cases, e.g. in the medical or automotive industries. Read more

Sep 21 2023

Renode 1.14 with ARMv8 support, improved co-simulation and new platforms

Renode 1.14 with ARMv8 support, improved co-simulation and new platforms

Antmicro is happy to announce the next, 1.14 release of our open source Renode simulation framework, including lots of new developments originating from both customer and R&D projects, along with community contributions. Since the last release, we’ve passed several important milestones such as adding ARMv8-A and 64-bit peripheral support in Renode and initial support for ARMv8-R. The 1.14 release also introduces Direct Programming Interface support, many new platforms including STM32WBA52 and the RISC‑V-based HiFive Unmatched, improvements in a wide range of peripherals, new exciting features and general fixes across the board. Read more

Sep 20 2023

DPI support in Renode for HDL co-simulation with Verilator and Questa

DPI support in Renode for HDL co-simulation with Verilator and Questa

Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The HDL source can also be used for high-fidelity, cycle-accurate simulation of your circuits, but at the cost of lower performance compared to functional simulation, which abstracts away much of the complexity. Read more