RISC-V vector instructions support in Renode

Published: December 6th, 2021

Building on top of the flexibility that was the original premise of Renode, our open source simulation framework has for some years now been used for pre-silicon development, architectural exploration and hardware-software co-design.

Using Renode for these kinds of use cases is especially popular in companies who have been encouraged by the open RISC‑V ISA to look for new, more software-driven approaches to developing new silicon, especially in the area of machine learning where much of the innovation is being driven by new software breakthroughs, and hardware races to keep up.

RISC‑V has been a major focus for Antmicro many years now, as hinted at by Antmicro becoming Founding member of the RISC‑V International (then Foundation) in 2015. Besides SoC implementations, tools, software and other open source IP projects that RISC‑V has been a steady source of for us, Renode was obviously bound to get RISC‑V support sooner rather than later.

A major milestone happened when our collaboration with Microchip (then Microsemi) was kicked off in 2017 (and continues to this day), and since then RISC‑V has also generated a large number of very interesting projects with customers and partners such as QuickLogic, Google, SiFive, Beagleboard and others. This in turn resulted in steadily improving support for RISC‑V and more flexibility around designing RISC‑V based systems using Renode. Now in collaboration with Google - based on even more exciting joint projects we are working on - we have expanded our RISC‑V support with the V extension, providing a range of instructions to operate on vectors of data.

Accelerating Machine Learning with RISC‑V

RISC‑V is a modular and extendible ISA which offers many options to silicon architects. For higher-performance, ML-oriented platforms it is typical to implement vector instructions. RISC‑V vector instructions, provided by the V extension, operate on registers of variable length (vectors), allowing you to perform the same operation across many data points with one instruction, e.g. allowing you to multiply a whole data vector in one go. They are very useful for accelerating repeatable operations, like the ones often performed in Machine Learning, and for other use cases where you need to crunch a lot of data.

The V extension adds 32 vector registers, v0-v31, on top of the base RISC‑V ISA. Besides the general registers, seven special CSRs are defined, used to control vector calculations and to let the software learn about the constraints of the hardware. This allows software engineers to easily develop portable code, dynamically adjusting the processing flow to fully benefit from the capabilities of the RISC‑V core.

Naturally, vector registers have to be handled with custom vector instructions. The ISA extension defines a range of these, allowing for operations on integer, fixed- or floating-point numbers, for very precise selection of vector elements, for their narrowing and widening and for much more.

RISC‑V V Extension

The complexity of the V specification, stemming from its flexibility to address a wide array of use cases, means it had to live through a series of iterations ironing out the details before reaching the current level of maturity. The V extension spec it is however now considered stable (frozen for public review in RISC‑V International's nomenclature) and is soon to be ratified as a full-grown RISC‑V ISA extension.

Renode support for vectors

Just as RISC‑V, Renode is very modular and allows you to run highly customized setups - with selected subsets of the ISA or even with custom CSRs and instructions. Support for the V extension is an important addition to Renode‚Äôs ML-oriented feature arsenal, following the addition of support for Custom Function Units and various metrics analysis and other features implemented as part of our work with the TensorFlow Lite Micro team.

Support for vector instructions in Renode follows the 1.0-rc1 version of the specification, adding all of the defined opcodes and registers. You can already try it out using our nightly builds or simply by building Renode from sources. This support is also going to be included in the upcoming 1.13 release.

Accelerating your development with Renode

The upcoming ratification of the 1.0 version of the RISC‑V V specification will soon let us see more and more physical RISC‑V platforms designed for efficient ML processing. An open source development framework will be an invaluable addition to everyday toolchain, allowing developers to release their solutions faster and in better quality.

Whether you are working on a new Machine Learning hardware platform, or you are developing ML software, Renode can help you in the whole life-cycle of your product, starting with design validation in the pre-silicon stage, through great debugging and tracing capabilities, to reliable testing and verification. If you'd like to use our commercial services to help you develop your custom Machine Learning solutions with Renode, please reach out to us at contact@renode.io.

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