As part of the effort to introduce open source tools and building blocks to ASIC development, together with other CHIPS Alliance members, Antmicro has been supporting the Multi-Project-Wafer (MPW) shuttle program, using the first open source 130nm PDK run by efabless, Google and SkyWater Technology Foundry. Making open tooling for pre-silicon testing and verification broadly available has significant potential for mitigating difficulties in the ASIC design of post-Moore’s Law age. In yet another push towards this direction, Antmicro has introduced an MPW design tester template for Renode, our open source simulation framework, targeted at open MPW shuttle submission projects.

First free and open source fabrication shuttle

The free and open source MPW program has opened up ASIC fabrication to everyone through manufacturing shuttles with submission windows every other month. Fabrication of the submitted designs is financed by Google and the designs must meet the following criteria:

• the ASIC design must be open-sourced
• the project must be designed with open-source tools
• each IC needs to fit within a unified user area (connected to a common harness)

So far, over 450 designs have been submitted to the shuttle in its 7 runs, with a variety of different ASIC building blocks, experiments, including at least 20 (mostly RISC‑V) CPUs among them. What is worth mentioning, 60% of the designs were submitted by first time designers, speaking to the shuttle’s approachability and confirming that the shuttles fill an important gap in the ecosystem. The original program is now followed by a new MPW Shuttle series using another open source PDK from GlobalFoundries released with Google’s help, the G180.

Difficulties in ASIC design testing

ASIC design flows imply long turnaround times and offer limited capabilities of rework for bug-fixing purposes, which unfortunately means significant costs of mistakes, both in terms of finances and lost time. On top of this, most ASICs "die" silently, without any telltale signs of failure. Another factor that adds to the risk of failure is that ASIC design is usually deadline-driven, which tends to push software development back towards the end of the process, often leading to further bugs being discovered at later stages, which aggravates the problem even further.

CHIPS Alliance, an Linux Foundation project grouping both industry heavyweights like Google, Microsoft and Intel as well as open source pioneers like Antmicro and efabless are trying to mitigate this problem by shifting the silicon industry’s focus towards open source tooling. As part of this broader initiative to open source ASIC design, together with customers like Western Digital and Google, Antmicro has been pushing for adding verification capabilities into open source Verilator simulator, better developer productivity tooling, open source ASIC-capable peripheral blocks such as DDR controllers and more. Now, expanding the portfolio of open source technologies targeted at ASIC design, we have been building out the Renode MPW Tester - a template for pre-silicon testing SkyWater MPW designs using Renode, Antmicro's open source simulation framework, in a co-simulation setup with Verilator.

Renode MPW tester overview

Basing on Renode’s HDL model co-simulation capabilities, the MPW tester template enables us to simulate the Caravel’s VexRiscv core-based management area along with its Wishbone bus in Renode, while simultaneously simulating the custom user area in Verilator, an open-source Verilog/SystemVerilog simulator which Antmicro is heavily contributing to. In order to make this possible, Renode provides an integration layer for Verilator as a plugin, enabling co-simulation of verilated peripherals. Dividing the project into a fixed part (the Caravel harness) with fast simulation in Renode, and a variable, user-specific part, with slower but more precise gate level simulation via Verilator makes it easier to focus on the latter, rapidly develop associated software and isolate potential problems. Renode’s Verilator integration supports various bus protocols, including AXI4, AXI4Lite and Wishbone, as well as allows interrupt and external interface connections, e.g. UART Rx/Tx lines. The connected design’s clock is driven by Renode, allowing full control over execution cycles of the verilated peripheral. Testing of larger, more complex systems, including multi-node setups, is also within the scope of Renode’s capabilities. Taking advantage of this functionality, we are currently working on enabling simulation of Caravel with an STM32-based development board that is now being shipped to MPW-2 participants to assist with bringup.

Testing real-life MPW designs

To illustrate a real-life use of the Renode MPW tester, we have simulated a public project design submitted to the sixth run of the MPW by Hanssel Morales - an AES core called fossiAES. We have generated a verilated peripheral based on the design and ran sample software in co-simulation with the Caravel SoC in order to verify the AES core’s function. Antmicro’s goal is to allow designers to fork the testing automation template repository and adjust it to their own needs by simply providing proper paths to their designs, test software and signal mapping.

Connecting to the Renode ecosystem

In order to connect designs to Renode, users can use the VerilogIntegrationLibrary included in Renode that provides implementations of buses and other connection layers. Sample verilated projects and building infrastructure are available in a separate repository. Within the framework, the CPU and peripherals on the SoC are represented by Renode Platform .repl files auto-generated from the SoC description, and the resources (e.g. a verilated peripheral) are defined by Renode Script .resc files. Both .repland .resc files are standardized for the MPW use case, since all designs use the same management SoC. With proper Renode integration, projects can benefit from a variety of Renode features, such as GDB integration, state saving, various protocol analysis and tracing tools, as well as - perhaps most importantly - standardized test automation with Robot.

Automated testing with Robot

For automated testing, Renode can be combined with the Robot Framework which is a text-based, easily extendible test framework that can generate useful and readable test reports. The Renode MPW Tester repository includes an example Robot test which gets executed in the project’s CI. A great illustration of the scalability of this approach is Antmicro’s Zephyr Dashboard, a cloud-based CI system combining structured Zephyr data and Renode’s flexibility and configurability to produce a concise dashboard, displaying Zephyr-compatible boards currently supported in the framework. A similar approach - running test payloads across the space of the MPW shuttle projects - could be foreseen for future runs of the free MPW shuttles, providing locally reproducible tests, interactive traces and logs, and resulting in a better success rate and reproducibility of the submissions.

Design ASICs more efficiently with Antmicro

The Renode MPW Tester enables easier software development for the MPW shuttle designs and comprehensive software validation prior to tapeout, potentially helping more users' submissions to be successful on their first try. The approach using Renode and Verilator for early software development as exemplified in the MPW tester could be translated to commercial settings in which your hardware and software teams can cooperate more closely throughout the entire ASIC development process. The tester is fully open source, which makes it easy to adapt for a wide range of MPW shuttle designs - and it is being further improved in collaboration with Google and efabless in terms of user experience and portability to other designs.

If you need commercial assistance with your own MPW shuttle project, or would like to discuss implementing open source, software driven verification/prototyping flows for your own ASIC development, do not hesitate to reach out to us at contact@antmicro.com.