Following the announcement of support for ARMv8-A and ARMv8-R ISAs earlier this year, Antmicro has now extended its Renode system simulation framework with initial support for Cortex-R5 and Cortex-R8 cores implementing the 32-bit ARMv7-R instruction set, thus expanding the already great coverage of the ARM architecture portfolio.

This development marks yet another important milestone for the framework, granting access to Renode’s extensive, automation-friendly testing ecosystem for real-time and safety-critical use case scenarios targeted by Cortex-R5 and Cortex-R8 chips.

Below, we share some of the intricacies of adding the support to Renode, show you how to simulate the real-time side of the Zynq UltraScale+ MPSoC (which features Cortex-R5 cores alongside the Cortex-A53 which were enabled earlier this year) in simulation, and run some Robot tests for that platform. As we continue to extend support for these cores, all new developments will be released as part of regular Renode updates.

Implementation overview

The work on enabling the two new cores partially inherits from and builds upon the support for 64-bit ARM hardware blocks added before, e.g. timers or interrupt controllers, as reuse is common across ARM cores. And since Cortex-R8, which was our primary target for this project, is pretty rare in general purpose devices out in the world, we developed support for it alongside the closely-related R5, for which the open source software offering is much wider.

The initial support focuses on the CPUs themselves, and more specifically basic ISA and key elements like the Memory Protection Units (MPU). Within this project, we are also extending multicore support by adding basic support for Tightly-Coupled Memory and overhauling ARM 32-bit atomic instructions.

Zynq UltraScale+: a real ARMv7-R target in Renode

In order to be able to test the initial implementation in practice, we created the respective platforms in Renode’s REPL configuration format: for Cortex-R8, out of necessity, it was a generic platform, but in Cortex-R5’s case we decided to recreate the Cortex-R5 part of the Zynq UltraScale+ MPSoC. AMD’s Zynq US+ platform packs two Cortex-R5 cores alongside dual or quad Cortex-A53 (depending on the variant), and has found its applications in a range of industries, from broadcasting, through mining, to space. Antmicro itself has been using the FPGA SoC in various Machine Learning and computer vision systems, and released a number of open hardware designs. For one of our projects, we also worked with enabling Zephyr on the platform. Its notable predecessor, Zynq 7000, has also been available in Renode for some time now.

Demos

The Zynq UltraScale+ platform is currently provided in two flavors - Cortex-R and Cortex-A, with plans to merge them into a single platform in the future. You can run the Cortex-R5 demo of the Zynq UltraScale+ board in simulation on your machine by running:

include @scripts/single-node/xilinx_zynqmp_r5.resc

For Cortex-R5, there is also a series of Zephyr and U-Boot based, automatic Robot Framework tests which you can run by executing the command below on your local machine:

renode-test tests/platforms/xilinx_zynqmp_r5.robot

Be sure to follow the progress in extending the support for ARMv7-R platforms using Antmicro’s Zephyr and U-Boot Dashboards or visit Renode’s GitHub repository where we regularly release new versions.

Build and test your ARM-based solutions with Renode

If you are using ARMv7-R CPUs in your devices, be it on their own or in heterogeneous setups, Antmicro can help you simulate these platforms as well as design, thoroughly test, and adapt software for your use cases, all thanks to the capabilities offered by Renode.

Feel free to contact us at contact@antmicro.com to discuss the ways Antmicro can use open source solutions to accelerate your work and put you in full control of your workflows.