Jan 19
2023
Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development use cases. Renode is a versatile simulation framework that allows you to easily run unmodified software inside simulated environments composed of highly-reusable building blocks representing components of a platform; co-simulation allows you to attach an externally created peripheral, e.g., built with Verilog to a Renode simulation to function as any other part of the simulated system. This allows you to iterate your hardware RTL development while benefiting from the infrastructure, feature set, and speed of Renode running the rest of the system on a functional level. Thanks to recent developments for our customers interested in even more control over their simulated environment driven by the needs of advanced RISC‑V silicon development, support for Verilator in Renode has been expanded to allow CPUs simulated directly from RTL, which opens an array of new possibilities for developing new CPU core IP and combining it with Renode’s vast portfolio of peripheral IP for a complete system able to run advanced software. Read more
Dec 29
2022
Originally issued by Microchip. Read more
Dec 21
2022
When deploying consumer-facing products which process multi-sensor data in the field it’s almost impossible to predict all possible scenarios. But massively scalable, reliable and deterministic testing in simulation can get you much closer to that ideal state. The open source Renode framework enables unprecedented levels of automated testing for hardware products, both in development and throughout the product’s lifecycle, by providing determinism and running production binaries just like on the target hardware. Renode supports hundreds of embedded platforms and comes with a range of developer-oriented features such as state saving and replaying, advanced hooks and events, comprehensive tracing, multi-core debugging, etc. Read more
Nov 24
2022
As part of the effort to introduce open source tools and building blocks to ASIC development, together with other CHIPS Alliance members, Antmicro has been supporting the Multi-Project-Wafer (MPW) shuttle program, using the first open source 130nm PDK run by efabless, Google and SkyWater Technology Foundry. Making open tooling for pre-silicon testing and verification broadly available has significant potential for mitigating difficulties in the ASIC design of post-Moore’s Law age. In yet another push towards this direction, Antmicro has introduced an MPW design tester template for Renode, our open source simulation framework, targeted at open MPW shuttle submission projects. Read more
Nov 14
2022
Antmicro’s open source Renode simulation framework offers support for the Bluetooth Low Energy (BLE) protocol and multi-node simulation capabilities, which makes it a great environment for development, debugging and testing of local area radio networks, such as IoT consumer devices, smart home applications or multi-sensor telemetry systems. On top of device-level debugging through virtual machine code execution, Renode features probabilistic packets loss simulation, global network state analysis and, perhaps most notably in this case, automated testing of various network configurations with the Robot Framework. Read more