What's new?

Mar 24 2022

Precursor: Renode for developing advanced products with embedded GUIs

Precursor: Renode for developing advanced products with embedded GUIs

Our open source Renode simulator has been helping our customers develop products using ARM, RISC‑V and - recently - Xtensa-based SoCs, providing hardware-software co-development and CI-driven testing capabilities for a variety of real product development projects. One of such projects, previously described on our blog, is Betrusted’s Precursor, an FPGA-based, fully open source, transparent and secure communication device based (among other things) on two interconnected RISC‑V CPUs. Read more

Mar 15 2022

Test-driven development of multi-node Zephyr + micro-ROS solutions with Renode

Test-driven development of multi-node Zephyr + micro-ROS solutions with Renode

Antmicro is actively involved in developing advanced applications, which may involve multiple subsystems communicating with each other, variable device configurations and various communication protocols. To handle such solutions, we often use the ROS (Robot Operating System) framework. It allows the developer to wrap the application’s subsystems in separate programs, called nodes. Nodes can communicate with each other in a publisher-subscriber (one-to-one) and client-service (one-to-one) manner. It helps create complex applications in a lean and modular way. Read more

Jan 28 2022

Adding Xtensa ISA support in Renode for the Sound Open Firmware project

Adding Xtensa ISA support in Renode for the Sound Open Firmware project

The Xtensa architecture, originally from Tensilica (now part of Cadence), is the base for a family of licensable, configurable cores, enabling easy customization.
This is especially useful in certain applications such as DSP (digital signal processing), and thereby audio, where careful fine-tuning of the processing core configuration alongside the firmware can yield concrete power and performance advantages which could decide the make or break of a product. Read more

Dec 6 2021

RISC-V vector instructions support in Renode

RISC-V vector instructions support in Renode

Building on top of the flexibility that was the original premise of Renode, our open source simulation framework has for some years now been used for pre-silicon development, architectural exploration and hardware-software co-design. Read more