May 16
2025
The Capability Hardware Extension to RISC‑V for Internet of Things (CHERIoT) project provides a hardware platform built around a modified RISC‑V Ibex core, designed for enhanced security through limited access of executed applications to individual components of the system. Developed by a group of commercial and university partners, it implements CHERI (Capability Hardware Enhanced RISC Instructions) for the RISC‑V ISA. Read more
May 7
2025
Native 64-bit Arm host support, which is now available for both Linux and macOS via dotnet portable packages, brings a significant efficiency improvement for developers running the Renode simulation framework on Mac workstations, but also paves the way for more complex use cases, such as running Renode on Arm-based server infrastructure. Read more
Apr 22
2025
When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation of elements of your design undergoing most heavy modifications with functional simulation using Antmicro's Renode framework for "best of both worlds" in terms of performance vs. accuracy. Read more
Feb 24
2025
Antmicro's automotive customers are using the versatile simulation capabilities of Renode for developing and testing multi-node systems to accelerate the transition towards software-defined vehicles. The framework offers determinism of execution and enables transparent debugging while easily integrating into existing tools and provides simulation models for hundreds of SoC and development board targets. Read more
Feb 6
2025
SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable source of truth, SystemRDL provides a basis on which you can build other assets, such as SystemVerilog designs, test suites, software (drivers), and documentation. Read more