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May 16 2025

Renode integration with MPACT-Cheriot for secure IoT systems simulation

Renode integration with MPACT-Cheriot for secure IoT systems simulation

The Capability Hardware Extension to RISC‑V for Internet of Things (CHERIoT) project provides a hardware platform built around a modified RISC‑V Ibex core, designed for enhanced security through limited access of executed applications to individual components of the system. Developed by a group of commercial and university partners, it implements CHERI (Capability Hardware Enhanced RISC Instructions) for the RISC‑V ISA. Read more

Apr 22 2025

Enabling complex HDL co-simulation scenarios using Renode's Direct Programming Interface support

Enabling complex HDL co-simulation scenarios using Renode's Direct Programming Interface support

When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation of elements of your design undergoing most heavy modifications with functional simulation using Antmicro's Renode framework for "best of both worlds" in terms of performance vs. accuracy. Read more

Feb 6 2025

Simplifying Renode model generation with SystemRDL-to-C# conversion

Simplifying Renode model generation with SystemRDL-to-C# conversion

SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable source of truth, SystemRDL provides a basis on which you can build other assets, such as SystemVerilog designs, test suites, software (drivers), and documentation. Read more