December 4th 2018, Santa Clara, CA - Today, Antmicro, a high-tech company focusing on introducing open technologies to modern edge computing systems and RISC‑V ecosystem leader, has announced adding support for the groundbreaking Linux-enabled PolarFire SoC revealed earlier by Microchip Technology in the revolutionary open source Renode software development framework. The announcement comes during the inaugural RISC‑V Summit currently taking place in Santa Clara, California.
Enabling the Freedom to Innovate with Hardware/Software Co-Design
Microchip PolarFire SoC is a new class of SoC FPGAs that combines the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC‑V ISA.
In a move that is the result of the ongoing strategic cooperation between Antmicro and Microsemi (a subsidiary of Microchip) around the latter’s Mi-V ecosystem, the new PolarFire SoC architecture is made available for developers worldwide in Renode today to accelerate the practical adoption of Linux-enabled platforms that are deemed crucial for the industry’s migration to RISC‑V.
By adding support for Microsemi’s PF SoC, Antmicro’s open source Renode enables pre-silicon software development for everyone, while Microchip and their customers gather feedback on real needs and see real first applications before chips are taped out. The approach introduces a unique perspective of driving hardware development with software, promoting scalability and collaborative design - the cornerstones of the RISC‑V movement which both Microchip and Antmicro, as Platinum Founding Members of the RISC‑V Foundation, are spearheading.
Renode 1.6 available now on GitHub
Renode’s latest release 1.6 is now available on GitHub. The current release, apart from adding support for the Microsemi PolarFire SoC processor subsystem (with PCIe controller, USB controller, QSPI flash, CAN, I2C, SPI and more), includes substantial upgrades to better accommodate RISC‑V systems: atomic instructions for RISC‑V, new USB and PCI infrastructure, block-finished event infrastructure (verified on both RISC‑V and ARM cores), as well as support for the PicoSoC RISC‑V softCPU.